VLSI Design

https://www.hindawi.com/journals/vlsi/

List of Papers (Total 298)

Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing

Built-in-self-test (BIST) response data can be compacted using a linear-feedback shift register (LFSR). Prior work has indicated that the probability of aliasing tends to converge to 2-k for a polynomial of degree k and large test length, and that primitive polynomials perform better than non-primitive polynomials. Nearly all analytical models and simulations have been based on...

High Throughput Error Control Using Parallel CRC

Redesigning the LFSR (Linear Feedback Shift Register) so that syndrome calculations can be performed in one sweep allows for fast error control in high speed computer networks. The resulting structure forms the basis of the PEDDC (Parallel Encoder, Decoder, Detector, Corrector) which replaces the conventional Serial Encoder, Decoder, Detector, Corrector for generation and...

A New Clustering Method Based on General Connectivity

In this paper, we present a novel concept of the general connectivity among cells. While conventional concept considers direct connections only, the new concept considers both the direct and indirect connections among cells leading to a model capturing a more precise relationship among cells. Based on the model, a new parallel clustering approach is proposed and analyzed. Another...

Area Optimization of Slicing Floorplans in Parallel

We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplan that respects a given slicing tree. The algorithm runs in O(n) time and requires O(n) processors, where n is the number of modules. It is based on a new O(n2) sequential algorithm for solving the above problem. We then present a parallel algorithm for finding a set...

Embeddings into Hyper Petersen Networks: Yet Another Hypercube-Like Interconnection Topology

A new hypercube-like topology, called the hyper Petersen (HP) network, is proposed and analyzed, which is constructed from the well-known cartesian product of the binary hypercube and the Petersen graph of ten nodes.

Input/Output Pad Placement Problem

We propose efficient heuristics for placing input/output (I/O) pads around the VLSI chip boundary. The heuristics are based on the circuit connectivity and do not require the placement of cells. This is useful for cell placement methods that require the knowledge of I/O pad placement. Using these heuristics, several pad placement candidates can be generated as input to cell...

A Comparative Study of Synchronous Clocking Schemes for VLSI Based Systems

Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The scheme guarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process clock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses a VLSI model to compare the properties of the new...

New Methods for the Construction of Test Cases for Partitioning Heuristics

Partitioning is an important problem in the design automation of integrated circuits. This problem in many of its formulation is NP-Hard, and several heuristic methods have been proposed for its solution. To evaluate the effectiveness of the various partitioning heuristics, it is desirable to have test cases with known optimal solutions that are as “random looking” as possible...

Hydrodynamic Models of Semiconductor Electron Transport at High Fields

Hydrodynamic or continuum descriptions of electron transport have long been used for modeling and simulating semiconductor devices. In this paper, we use classical field theory ideas to discuss the physical foundations of such descriptions as applied specifically to high-field transport regimes. The classical field theory development of these types of models is of interest...

Design and Implementation of a Low Power Ternary Full Adder

In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their...

Hardware Design Rule Checker Using a CAM Architecture

This paper presents a hardware implementation of design rule checker using a specialized Content Addressable Memory(CAM) for the Manhattan geometric designs. Two dimensional relationships between rectangular objects in a design are checked with one dimensional design rules. The input data is processed by the pixel pre-processor in such a way that direct comparison between the...

A Novel Path Delay Fault Simulator Using Binary Logic

A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach...

On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach

Genetic Algorithms are robust search and optimization techniques. A Genetic Algorithm based approach for determining the optimal input distributions for generating random test vectors is proposed in the paper. A cost function based on the COP testability measure for determining the efficacy of the input distributions is discussed. A brief overview of Genetic Algorithms (GAs) and...

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

In this paper, we discuss the controllability and observability issues in bilateral bit-level systolic arrays. We have introduced a new concept—‘Sj-controllability in M steps’, which is somewhat analogous to the concept of C-testability and refers to the fact that all the cells in the array can be set to the state Sj in at most M steps after initialization. Systolic arrays where...

Erratum

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly...

A New Theory for Testability-Preserving Optimization of Combinational Circuits

Testability should be considered as early as possible in VLSI synthesis and optimization. In most CAD tools, testability preservation is achieved as a by-product of finding a less redundant implementation. Unfortunately, this approach is not supported by theory. It is essential to have an optimization scheme that systematically preserves testability. A complete theory covering...

TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis

In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic...

Lattice Effects in the Complex Subband Dispersion of 2DEG Semiconductor Waveguide Structures Subjected to a Perpendicular Magnetic Field

In modeling waveguide magneto-transport experiments (in a quasi-two dimensional electron gas), it is important to have knowledge of the electronic states in a magnetic field perpendicular to the plane of the waveguide confinement potential. We present numerical results, within a lattice model, for the full complex subband dispersion of a rectangular waveguide. The form of our...

A Lattice Boltzmann Scheme for Semiconductor Dynamics

We discuss an extension of the Lattice Boltzmann method which may prove useful for the numerical study of electron transport in semiconductors.

A New Concept for Solving the Boltzmann Transport Equation in Ultra-fast Transient Situations

A concept based on relaxation of the hydrodynamic parameters is introduced to arrive at a computational model for the extreme non-equilibrium distribution function of carriers in multi-valley bandstructure. The relaxation times are taken to describe the evolution scale of the distribution function. The developed model is able to account for transport phenomena at the momentum...

Recent Advances in Device Simulation Using Standard Transport Models

In this paper we address a number of issues related with device simulation in 3-D, and point out a few deficiencies which still prevent 3-D device simulation to be widely accepted as a standard tool for device design and optimization in an engineering environment. More specifically, such deficiencies have to do with structure definition and mesh generation, as well as with the...

Self-Consistent Solution of the Multi Band Boltzmann, Poisson and Hole-Continuity Equations

The Boltzmann transport equation (BTE) for multiple bands is solved by the spherical harmonic approach. The distribution function is obtained for energies greater than 3 eV. The BTE is solved self consistently with the Poisson equation for a one dimensional npn bipolar junction transistor (BJT). The novel features are: the use of boundary fitted curvilinear grid, and Scharfetter...

Numerically Absorbing Boundary Conditions for Quantum Evolution Equations

Transparent boundary conditions for the transient Schrödinger equation on a domain Ω can be derived explicitly under the assumption that the given potential V is constant outside of this domain. In 1D these boundary conditions are non-local in time (of memory type). For the Crank-Nicolson finite difference scheme, discrete transparent boundary conditions are derived, and the...