A New Design Methodology for Two-Dimensional Logic Arrays
International Journal of
A New Design Methodology for Two-Dimensional Logic Arrays
NING SONG Lattice Semiconductor Corporation 0 1
McCarthy Blvd. 0 1
Milpitas 0 1
0 ANDISHEH SARABI Viewlogic Systems, Inc. , 47211 Lakeview Blvd., Fremont, CA 94538 , USA
1 MAREK A. PERKOWSKI and MALGORZATA CHRZANOWSKA-JESKE Portland State University, Department of Electrical Engineering P. O. Box 751, Portland, OR, 97207 , USA
This paper introduces a new design approach that combines stages of logic and physical design. The logic function is synthesized and mapped to a two-dimensional array of logic cells. This array generalizes PLAs, XPLAs and cellular Maitra cascades. Each cell can be programmed to a wire, an inverter, or a two-input AND, OR or EXOR gate (with any subset of inputs negated). The gate can take any output of four neighbor cells and four neighbor buses as its inputs, and sends its result back to them. This two-dimensional geometrical model is well suited for both fine-grain FPGA realization and sea-of-gates custom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly shaped structure of (mostly) locally connected cells. Two stages: restricted factorization, and column folding, are discussed in more details to illustrate our general methodology.
Cellular FPGAs; Maitra Arrays; Multi-level Representation; Factorization; Folding
-
INTRODUCTION
ate arrays and standard cells are currently the most
popular technologies used in ASIC design. On the
other hand, the two level Sum-of-Products (SOP)
structure is widely used in Programmable Logic Devices
(PLDs). For two-level logic, there are effective synthesis
tools for both SOP minimization [
23
] and
ExclusiveSum-of-Products (ESOP) minimization [
25,28
]. While
the standard PLA is composed of an AND plane for
product terms, and an OR collecting (output) plane, the
recently introduced XPLA (Exor PLAto[25]) has an
AND plane for product terms and an EXOR collecting
plane. Another advantage of the two-level SOP or ESOP
implementation is that the difficult placement and routing
problems, inherent to gate array and standard cell
technologies, are avoided.
The two-level approach, although commonly used in
the PLD technology, requires large area and leads to low
performance when applied to larger circuits. On the other
hand, multiple-level-logic gate arrays and standard cell
realizations can have high performance and consume a
smaller area. The multiple-level-logic design, however,
is much more difficult, both on the logic level and on the
physical design level (placement and routing). Using
architecture constraints during logic synthesis could
decrease complexity of the physical design stage. But
until very recently not much has been published on
combining the logic and physical design stages.
Therefore, as the result of the above trade-off, there is
an increased interest in developing new FPGA
architectures that would combine the power and flexibility of
multi-level circuits with the regularity and ease of use of
logic based on two-level expressions. Two approaches:
fine-grain FPGAs and Complex PLDs (CPLDs), have
been recently proposed. CPLDs have partitioned PLA/
PAL arrays connected by global routing channels.
Finegrain FPGAs have been developed by Concurrent Logic
[
5,6
] (now Atmel [2]), Algotronix [
1
] (now Xilinx),
Pilkington 14], Motorola 16], Plessey, Apple, Toshiba,
and National Semiconductor. Although quite different in
details, these fine-grain FPGA architectures have some
very specific common properties.
Below we will create a generic model of a
"twodimensional logic array" that includes most of the
important properties of these fine-grain FPGA
architectures. Although quite simple, the model is also well
suited for custom ASIC design in sea-of-gates or similar
technologies.
A very practical and interesting research problem
related to new programmable architectures is to find
some scientific evidence and experimental confirmation
with respect to merits of the existing fine-grain
architectures: how "good" are they? can they be improved? how?
To our knowledge, while designing these architectures
([
14
] being the only exception), there was no research on
selecting the best cells’ functionality, their connection
patterns, a number and location of buses, etc. The
architectures were created purely on the "try and error"
principle, with several modifications in next chips’
generations and software redesigns. It is then very important
to create new general methodologies and related
prototyping software to help design new fine-grain
architectures. We propose here such a methodology and related
software. We will call it the "Fine-Grain FPGA
Designer’s Work Bench".
Our approach to create optimal fine-grain FPGA
architectures is through the Device and Algorithm
CoGeneration. Conventionally, the devices are designed
first. Next, the optimization methods are created to
support the (...truncated)