A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication

PLOS ONE, Dec 2019

A Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-Pass-Mesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-Pass-Torus is an efficient candidate among its predecessor’s and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication.

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A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication

December A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication Usman Ali Gulzari 2 3 Muhammad Sajid 2 3 Sheraz Anjum 1 3 Shahrukh Agha 2 3 Frank Sill Torres 0 3 0 Department of Electronic Engineering, University of Minas Gerais , Minas Gerais , Brazil 1 Department of Computer Science, COMSATS Institute of Information Technology , Wah Cantt , Pakistan 2 Department of Electrical Engineering, COMSATS Institute of Information Technology , Islamabad , Pakistan 3 Editor: Houbing Song, West Virginia University , UNITED STATES A Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-PassMesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-PassTorus is an efficient candidate among its predecessor's and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication. - OPEN ACCESS Data Availability Statement: All relevant data are within the paper. Funding: The authors received no specific funding for this work. Competing Interests: The authors have declared that no competing interests exist. Introduction The growing complexity of System-on-Chip (SoC) designs, characterized by an increasing number of Processing Elements (PEs), requires intelligent solutions for on chip communication. In alignment with this challenge, Networks-on-Chip (NoC) is emerging as a new and promising paradigm that targets an efficient communication between PEs [ 1 ]. NoC-based systems appear as an enhanced solution, as an evolution of flexibility, multitasking parallel computing, data capacity and scalability for future on-chip communications [ 2 ]. It uses packet switching and routing technology to reduce power consumption, to improve reusability, reliability and performance [3±4]. Customarily, topology is an important factor in a design which affects the overall performance of the NoC [5±6]. The efficient design of topology plays a role as a backbone to the complete NoC structure [ 7 ]. Topology design not only reflects the connection of each module distribution, it is also responsible for data transmission on chip [ 8 ]. Therefore, topology design plays an essential role in the performance of on chip communication network [ 9 ]. The performance of latency, throughput and other parameters are mainly dependent on the hop counts by a packet which traverses from source to its destination in the designed network. A topology has high impacts of power, energy, latency and throughput, but also on the routing and mapping strategy [10±13]. Principal issues to be addressed in NoC are reduction of power consumption and energy utilization at low penalties in performance, latency and throughput [ 14 ]. Further issues are network scalability and design complexity of routing elements [15±16]. The most promising and widely applied NoC topology is the so-called Mesh, which profits from a regular and simple structure [ 17 ]. However, Mesh networks suffer under poor scalability for large amount of PEs due to the great number of multi-hop links needed to provide complete reachability [ 18 ]. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to reduce the network diameter and increase the bisection width that in turn improves the overall performance of the network. Some alternative solutions are Meshes with hierarchical topologies like D-Mesh and D-Torus [ 19 ], which reduce the average hop count in the NoC. However, proposed structures lead to increased router complexity as well as higher costs in terms of power and energy consumption [20±21]. This paper (...truncated)


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Usman Ali Gulzari, Muhammad Sajid, Sheraz Anjum, Shahrukh Agha, Frank Sill Torres. A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication, PLOS ONE, 2016, Volume 11, Issue 12, DOI: 10.1371/journal.pone.0167590