Quantitative monitoring of STL with edit distance
Quantitative monitoring of STL with edit distance
Stefan Jakšic´ 0 1 2
Ezio Bartocci 0 1 2
Radu Grosu 0 1 2
Thang Nguyen 0 1 2
Dejan Nicˇkovic´ 0 1 2
B Stefan Jakšic´ 0 1 2
Radu Grosu 0 1 2
Thang Nguyen 0 1 2
0 Infineon Technologies AG , Siemensstraße 2, 9500 Villach , Austria
1 Faculty of Informatics, TU Wien , Treitlstraße 3, Vienna , Austria
2 Austrian Institute of Technology , Donau-City-Straße 1, Vienna , Austria
In cyber-physical systems (CPS), physical behaviors are typically controlled by digital hardware. As a consequence, continuous behaviors are discretized by sampling and quantization prior to their processing. Quantifying the similarity between CPS behaviors and their specification is an important ingredient in evaluating correctness and quality of such systems. We propose a novel procedure for measuring robustness between digitized CPS signals and signal temporal logic (STL) specifications. We first equip STL with quantitative semantics based on the weighted edit distance, a metric that quantifies both space and time mismatches between digitized CPS behaviors. We then develop a dynamic programming algorithm for computing the robustness degree between digitized signals and STL specifications. In order to promote hardware-based monitors we implemented our approach in FPGA. We evaluated it on automotive benchmarks defined by research community, and also on realistic data obtained from magnetic sensor used in modern cars.
Weighted edit distance; Robustness; Hardware monitors; Runtime verification; Dynamic programming
1 Introduction
Cyber-physical systems (CPS) integrate heterogeneous collaborative components that are
interconnected between themselves and their physical environment. They exhibit complex
behaviors that often combine discrete and continuous dynamics. The sophistication,
complexity and heterogeneity of CPS makes their verification a difficult task. Runtime monitoring
addresses this problem by providing a formal, yet scalable, verification method. It achieves
both rigor and efficiency by enabling evaluation of systems according to the properties of
their individual behaviors.
In the recent past, property-based runtime monitoring of CPS centered around signal
temporal logic (STL) [
29
] and its variants have received considerable attention [
2,6,7,14,
15,18,31
]. STL is a formal specification language for describing properties of continuous
and hybrid behaviors. In its original form, STL allows to distinguish correct from incorrect
behaviors. However, the binary true/false classification may not be sufficient for real-valued
behaviors. The classical satisfaction relation can be replaced by a more quantitative robustness
degree [
14,15,18
] of a behavior with respect to a temporal specification. The robustness
degree provides a finer measure of how far is the behavior from satisfying or violating of the
specification.
Here we propose a novel quantitative semantics for STL that measures the behavior
mismatches in both space and time. We consider applications in which continuous CPS behaviors
are observed by a digital device. In this scenario, continuous behaviors are typically
discretized, both in time and space, by an analog-to-digital converter (ADC). As a consequence,
we interpret STL over discrete-time digitized behaviors.
We first propose the weighted edit distance as an appropriate metric for measuring
similarity between CPS behaviors. The weighted edit distance has the following desirable
characteristics:
1. It is cumulative, hence it can differentiate between a single and multiple deviations from
a reference behavior;
2. It combines spatial and temporal aspects, which are both important when reasoning about
CPS behaviors; and
3. It is defined in discrete time, which is an important aspect for the applications that we
consider.
We then provide the quantitative semantics for STL based on this distance and discuss the
effects of sampling and quantization on the distance value. We develop an efficient online
algorithm for computing the robustness degree between a behavior and an STL formula. The
algorithm can be directly implemented both in software and hardware. In the former case,
the implemented procedure can be connected to the simulation engine of the CPS design and
used to monitor its correctness and quality. In the latter case, the resulting implementation
can be deployed on the Field Programmable Gate Array (FPGA) and used to monitor real
systems or design emulations. We implement the above procedure in Verilog and evaluate it
on an automotive benchmark.
We now discuss the main contributions of this work. In contrast to the previous research
on STL robustness, we adopt a sampled-time automata-based approach. This choice has
several important consequences. First, it allows direct and uniform implementation of STL
robustness monitors in both software and hardware and naturally enables monitoring in
realtime. We implement the algorithms in Verilog and deploy (...truncated)