Double Vivaldi antenna for wireless optical networks on chip
Opt Quant Electron
Double Vivaldi antenna for wireless optical networks on chip
Giovanna Calò 0 1 2 3
Gaetano Bellanca 0 1 2 3
Ali Emre Kaplan 0 1 2 3
Paolo Bassi 0 1 2 3
Vincenzo Petruzzelli 0 1 2 3
Giovanna Calò 0 1 2 3
0 Department of Engineering, University of Ferrara , Via Saragat, 1, Ferrara 44122 , Italy
1 Dipartimento di Ingegneria Elettrica e dell'Informazione, Politecnico di Bari , Via Orabona, 4, Bari 70125 , Italy
2 Guest Edited by Bastiaan Pieter de Hon, Sander Johannes Floris , Manfred Hammer, Dirk Schulz, Anne-Laure Fehrembach
3 Department of Electrical, Electronic and Information Engineering, University of Bologna , Viale del Risorgimento, 2, Bologna 40136 , Italy
In this paper we present a double plasmonic Vivaldi antenna for on-chip optical wireless communication. The proposed antenna is a two-element broadside array fed by a silicon waveguide. The designs of the power splitter and of the hybrid Si-plasmonic coupler used for antenna excitation are described in detail. The array radiation characteristics are optimized through Finite Difference Time Domain simulations and the performance of a point-to-point link is evaluated. The proposed double Vivaldi array increases the gain of 3 dB with respect to a single antenna, improving the received power on a link of 6 dB when the double antenna is used for both transmitting and receiving sections.
Optical antennas; Antenna array; Nanophotonics; Surface plasmons; Wireless optical communications; Optical networks on chip
1 Introduction
Chip Multiprocessors (CMPs), that exploit the potentialities of parallel computing, are
the state of the art solution to face the constant need of increasing the computing system
efficiency. A CMP consists of several smaller processing cores designed and replicated
several times. They achieve performance gain through parallel code execution using
multiple threads across the cores. As the number of cores in CMPs continues to scale, the
efficient interconnection of these cores is becoming a major challenge, to avoid
communication bottleneck and to meet the high bandwidth, low-power and low-latency
requirements which, actually, cannot be matched by traditional point-to-point connections through
dedicated wires. Network-on-chips (NoCs) have emerged as a technology enabling a high
degree of integration in multi-core systems on chip
(Benini and Micheli 2002)
. The NoCs
were introduced to reduce the wiring complexity and to increase communication efficiency
by designing regular topologies. However, an important performance limitation in
traditional NoCs, which are mainly made by switching elements, network interfaces and
interswitch links, arises from multi-hop communications based on planar metal interconnects
and to the consequent high latency and power consumption. In fact, at the physical level,
the metal interconnects are responsible for depressing the on-chip data bandwidth while
consuming an increasing percentage of power. Different approaches have been investigated
to overcome these limitations which range from integrated optics to wireless on-chip
communication. Architectures based on Optical Network-on-Chip (ONoC) rely on an optical
layer, stacked with electronic layers, that allows the communication between different cores
in the optical domain
(Beausoleil et al. 2008; Shacham et al. 2008; Miller 2009)
.
Optical networks significantly improve electronic technology, but at the expenses of complex
layout, sophisticated routing algorithms, and high power budget. Moreover, as the network
size scales up, signal losses and crosstalk due to waveguide crossings dramatically increase
(Gambini et al. 2015; Fusella and Cilardo 2016; Ortin-Obon et al. 2017)
. An alternative
emerging technology to overcome performance limitations of traditional NoCs is the
Wireless Network-on-Chip (WiNoC), which exploits on-chip wireless transmission to perform
an hybrid wired/wireless communication. In this approach silicon integrated antennas
replace wired channels, so that transmission performance, power consumption and long
distant communication problems of traditional wired NoCs can be addressed
simultaneously
(Lin et al. 2007; Ganguly et al. 2011; Deb et al. 2012; Matolak et al. 2012)
. Recent
research has established characteristics of silicon integrated antennas operating in the
millimeter-wave range of a few tens to one hundred gigahertz to be used for intra- and
interchip communication. On-chip wireless communication links alleviate not only the latency
issues of conventional technologies, but also the topological constraints. As a counterpart,
on-chip antennas operating in the millimeter-wave range of a few tens to one hundred
gigahertz suffer for low integrability and are not always viable solution at the CMP
communication level; therefore, higher operating frequencies, at least in the THz range, should be
required to reduce the size of the radiating elements
(Matolak et al. 2012; Lee et al. 2009)
.
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