Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics

Active and Passive Electronic Components, Sep 2019

In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.

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Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics

International Journal of IMPACT OF THE STRESS ON THE SUB-MICRON N-METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR CHARACTERISTICS R. MARRAKH 0 A. BOUHDADA 0 0 Laboratoire de Physique des MatOriaux et de Microdlectronique-UniversitO Hassan H Ai'n Chok Facult( des Sciences , Kin8, Route d'El Jadida, BP 5366 Madr(f-Casablanca- Morocco In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time. Hot-carrier-injection; Stress time; Drain current; Transconductance; MOSFET - I. INTRODUCTION The degradation of the NMOS transistors caused by hot carrier injection in the oxide and at the Si-SiO2 interface constitutes a potential limit to device scaling. Indeed, the transistor miniaturization entails the presence of higher electric fields that provide enough energy to the channel electrons which may generate electron-hole pairs through impact ionization. These electrons and holes contribute to the gate and substrate current [1-5] and they may create damage in the oxide or in the interface near the drain junction [6-8]. Due to its strong impacts on device and circuit reliability, the hot-carrier effect becomes an important research topic for submicrometer and deep submicrometer MOSFET devices. Understanding the physical phenomenon of the degradation process is required in order to find technological solutions to minimize the aging effect and device performance degradation. In this work we devote our effort to develop a drain current model in relation with the defect density generated by the hot-carrier-injection during stress time. This defect density is modeled by a spatio-temporal distribution. The modeling of this defect density was developed in our previous work [9] by investigating the threshold voltage evolution according to stress time. Simulation results allow us to deduce the impact of the stress time on the I-V characteristic and on the transconductance. II. DRAIN CURRENT MODELING To consider the source and drain resistances, we treat the device as an intrinsic MOSFET in series with two ones (Fig. l). Source damaged zone < AL > Gtae L G S S1 D1 D FIGURE Schematic diagram and equivalent circuit of MOSFET. The source drain voltage can be written as: VDS VD,S, + (Rs -[- RD)IDs The drain current expression in the linear region is given by: lz)s ,,WOCox[Vs Vro + zxvv- rV(y)] where p., W, Cox and Vas, are respectively, the surface mobility, the channel width, the gate oxide capacitance per unit area and the gate bias. 0 is the carrier velocity which is expressed by" where V(y) and Ey are the potential and the lateral electric field in the channel; 0sat is the carrier saturation velocity. The parameters involved in Eqs. ( 2 ) an ( 3 ) are defined as: ( 2 ) ( 3 ) 0 q =l -1--Ey/Esa 0sat Vro VFB + 2f + V/2dpf + VsB ,s- [ + o(vs- vr0)] +1 x v 8S XcepCox 02V(y) (Xe + i- ] Oy VFB VSB,s, and f are the flat-band voltage, the substrate bias, the dielectric permittivity and the Fermi potential, respectively. /% is the low field channel mobility and 0 is the mobility degradation factor resulting from vertical electric field. Xdep is the depletion width. A Vr is the threshold voltage reduction due to the lateral electric field. In the linear region A Vr is small and can be regarded as a constant since the lateral electric field is weak. The defect density created during stress time leads to an increase of the threshold voltage and a reduction of the carrier mobility, namely: 0 and/3 are fitting constants. Nit(y, ts) is the defect density created during stress, it is modeled [9] by: Nit(y, ts) Vth Vr0 + q -r-’o /0 [1 +O(Vcs- Vro)][1 +/3Uit(y, ts)] Nit(y, ts)= Nitmax(t) exp(’-(y2tr(ts)2-yc)2’) " / Nitmax ts t(ts) S;, Vt t (I)" a a0 + b log(ts) ( 4 ) ( 5 ) ( 6 ) ( 7 ) Vcs, (y) W is the channel width, los is the drain current. Se 10-15 cm2 is the average capture cross section, Vt- 107 cm/s is the thermal velocity, the exponent n has been found to range between 0.5 and 0.75 [10,11]. In our simulation it is taken equal to 0.5. tr0 is regarded as an effective impact ionization length [12]. Using Eqs. (1)-( 6 ) drain current: los WltsCox[V6s- Vth + AVT- FB(Vcs,(y) + RIos)]Ey los _Vtl,- VT"o /" - Vh + A Vv VD, s, L + VD & + s WCox RsFB VDS, Esat q Nit (y, t. Cox [1 +O(VGs-- VT0)][1 +/3Nit(y, ts)] Integrating Eq. ( 8 ) from y =0 to y--L and assuming that dVcs, dVcs, /dydy VD, S, /L, we obtain: The spatial average of the defect density Nit(y, t.) expressed as" where erf denotes the error function. From Eq. (l l) we can write VD& as: I/rOlS1 -V2 4v, v/V 2V ( 10 ) ( 11 ) ( 13 ) [JWCox[Vas Vt-’- + AVr- FRfls] By substituting Eq. ( 14 ) in (l), the drain current in the linear region can be expressed as: Is -/2 V/I22 2I 4I/3 where V, V2 and V3 are given by the following expressions: V V3 tFn WCo 2 IDS Esat IosL (16) When Vzs increases, the carrier velocity reach the saturation for high Vs values. The saturation channel voltage Vdsat is derived by letting Eq. ( 8 ) equal to the expression ( 10 )’ Vdsat -z The saturation current Ldsat is determined while replacing VDS with Vdsat in Eq. ( 10 ): The saturation extrinsic drain voltage Vdsat can be expressed as: Zs--Z3 C ots)) Z 2Z2 (ZI qii,-(-ov-,xi,)) Nit(L, /,/sat fis WCox VGS Vth qt_ A VT Vdsat Vdsat L + Vdsat + fis mCox RsFB Vdsat Esat A is a fitting parameter that is extracted from experimental data. When VDS becomes greater than Vd,at, the pinch-off region increases which results in a reduction of the channel length toward Left--L-AL. To determine the modulated channel length, we (18) FBLEsat (19) (20) (21) assume that the inversion charge is a constant in the saturation region. Hence, Eq. ( 8 )can be written as: 02 VCSl Oy: k ’2 [(VDsF- (Rs + Rd)IDs) AW U,(y. t) N,(L. t)] (22) CoxFe The boundary conditions at the pinch-off points are: k,2 k2FB Vcs, (y E(y Leff) VDS:Z- (Rs + Rd)IDs Left) Esat (1 + flNit (Left)) Using Eq. (23), the resolution of Eq. (22) gives the channel potential in the saturation region: Vcs, (Y) Esat VDse-- (Rs + Rd)IDs) +---(1 + Nit(Left))sinh(k’(y- Left)) +q A Vr Nit (y, ts (cosh (k’ (y Left) CoxFs +k’ eft q Nit(y’,t.) sinh(k’(y- y’))dy’ CoxFB Known that, Vcs, (y L) Vos- (Rs + Rd)IDs, numerical resolution of Eq. (24) gives AL. Replacing L by L- AL and Vos by VOSF in Eq. (16), provides the drain current. III. SIMULATION RESULTS The parameters of the transistor used in the simulation are given in Table I. (23) (24) TABLE Parameters L W Tox NA 0 fl lao Zgsat Values Variation of the los- VDs characteristic versus stress time. 2O 15 ’i L=0.61xm ’To14nm ........ W---40tm ;:::..:...::: 1016C__.3 _...:i:%’.7 m/..:;;;. X=0" 15 lamii:i:’;"’ V".GS=5 V". ............. ;i;" ./;.......-.."...’. ’";’" 0 ".," " nificant. Moreover, after pinch-off, the channel current is governed by the inverted channel between the source and the drain pinch-off, so it becomes virtually independent of the region between the pinch-off point and drain junction. Since the defects are mostly located in this region near the drain, its influence upon the drain current becomes less in saturation. Figure 3 shows the variation of the drain current drift versus stress time for different drain bias. The degradation of the drain current drift increases with stress time. Also notice that the degradation the delta decrease when the drain bias increase. 111.2. Impact on the Transconductance The curves of Figure 4 show that the stress acts on the transconductance, which decreases with, the stress time. The degradation of the transconductance is due to the mobility reduction caused by the increase of the defect density during stress time. This transconductance degradation is reduced as the gate voltage increase. Indeed, when the 1,4 L=h.6,"m 1,2 To= 14m W=401m NA=6.5 106crri J=O.151am 0,8 Vas--3V 0,6 0,4 0,2 0,0 0 stress con’ditins Vos=2.3 V VDS----6.5 V DS----’2 3V 4V L=0.6pm Tox=14nm -W=40pm NA=6.5 10TMcm" Xj=0.15pm Gate bias Vs (V) T,=tres 1.10’s Tstress-5.10’ s Tstres=l. 105S 3 4 gate voltage increase, the carrier density in the inversion layer increase and the effects of coulomb scattering are reduced by the screening effect. Thus, the degradation of transconductance is less significant. Exhibit The evolution of the ratio, between the transconductance drift Agm and the transconductance initial value gmo (before stress), versus stress time is sketched on Figure 5. This figure show that the evolution of the Ag,,,/gmo is linear, in logarithmic scale, what is qualitatively agree with the results given in the literature [13-15]. IV. CONCLUSION The modeling of the current drain in relation with interface defects created during stress time is very important. Since, it allows us to understand the aging phenomenon and the amount degradation of the performances of the devices. The simulations results show that the stress leads to the degradation of the I-V characteristic and the re0,1 0,01 L=0.61xm To14.1nm W-2Olm NA=1.1017 cni3 Stress conditions" V. =2.3 V VD=6.5 V 102 103 Stress time (s) 10 105 duction of the transconductance. The model can be applied to the simulation of device behavior after stress in order to improve the circuit long-term reliability. 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R. Marrakh, A. Bouhdada. Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics, Active and Passive Electronic Components, DOI: 10.1155/2001/18731