HW/SW co-design on embedded SoC FPGA for star tracking optimization in space applications

Journal of Real-Time Image Processing (2024) 21:16 https://doi.org/10.1007/s11554-023-01391-8 RESEARCH HW/SW co‑design on embedded SoC FPGA for star tracking optimization in space applications Vasileios Panousopoulos1 · Emmanouil Papaloukas1 · Vasileios Leon1 · Dimitrios Soudris1 · Emmanuel Koumandakis2 · George Lentaris1,3 Received: 8 August 2023 / Accepted: 26 November 2023 / Published online: 4 January 2024 © The Author(s) 2024 Abstract Star trackers are crucial for satellite orientation. Improving their efficiency via reconfigurable COTS HW accommodates NewSpace missions. The current work considers SoC FPGAs to leverage both increased reprogramming and high-performance capabilities. Based on a custom sensor+FPGA system, we develop and optimize the algorithmic chain of star tracking by focusing on the acceleration of the image processing parts. We combine multiple circuit design techniques, such as low-level pipelining, word-length optimization, HW/SW co-processing, and parametric HLS+HDL coding, to fine-tune our implementation on Zynq-7020 FPGA when using real and synthetic input data. Overall, with 4-MPixel images, we achieve more than 24 FPS throughput by accelerating >95% of the computation by 8.9×, at system level, while preserving the original SW accuracy and meeting the real-time requirements of the application. Keywords Star trackers · Space applications · COTS · SoC FPGAs 1 Introduction Space applications demand precise and real-time measurement of the satellite’s orientation. The use of star trackers [7] has been established as a common approach to fulfill such needs. These instruments consist of a camera sensor Vasileios Panousopoulos and Emmanouil Papaloukas have contributed equally to this work. * Vasileios Leon Vasileios Panousopoulos Emmanouil Papaloukas Dimitrios Soudris Emmanuel Koumandakis George Lentaris 1 National Technical University of Athens, Athens, Greece 2 Infinite Orbits, Toulouse, France 3 University of West Attica, Egaleo, Greece capturing sky images and a customized digital hardware, which detects the stars on these images, analyzes the stars’ relative positions, and determines the satellite’s three-axis attitude in the inertial space. This information is provided to the Vision-Based Navigation (VBN) systems of the spacecraft. Besides achieving arcsecond levels of accuracy in attitude determination, star trackers are employed to obtain centroids of Resident Space Objects (RSOs) and perform angles-only navigation for satellite rendezvous and formation flying. This use-case has been demonstrated in a number of satellite missions, such as AVANTI [10] and PRISMA [3]. The large amount of sensor data makes the task of detecting objects computationally intensive and, therefore, star tracking on general-purpose embedded processors becomes quite challenging. The trend of utilizing Commercial OffThe-Shelf (COTS) accelerators in space [20] has led us to examine such a solution in our proposed architecture, i.e., to combine a high-resolution camera with a high-performance COTS System-on-Chip (SoC) FPGA. In general, FPGAs are already utilized toward improving the performance of space avionics, as they outperform the conventional radiationhardened CPUs by order(s) of magnitude in terms of speed and power efficiency [15]. In particular, the space community employs both space-grade [18, 19, 22] and COTS [20, Vol.:(0123456789) 16 Page 2 of 13 Journal of Real-Time Image Processing (2024) 21:16 26, 34] FPGAs (e.g., AMD/Xilinx Zynq), for both acceleration and control purposes; various hybrid architectures exist [4, 16, 17] that include FPGAs for I/O handling, data transcoding, data compression, and general digital signal processing. In this work, we customize the star tracking on a COTS SoC FPGA platform while focusing on the optimization of its centroiding task and the necessary preprocessing operations of the algorithmic pipeline (pixel binning and clustering). Namely, we accelerate the precise estimation of the stars’ position in night sky images. The proposed HW/ SW embedded system utilizes both the Programming System (PS) and Programmable Logic (PL) of AMD/Xilinx’s Zynq-7020, as well as AMBA AXI protocols for PS–PL communication. Our system supports dynamic adjustment of image thresholding, it exploits parallelization at multiple levels via parametric circuit design, it thoroughly examines two distinct centroiding algorithms with certain trade-offs in accuracy and complexity. Furthermore, we implement the respective hardware models using both Hardware Description Language (HDL) and High-Level Synthesis (HLS) / C++ to perform extensive design space exploration and determine the most efficient solution. The experimental results show speed-up factors in the area of 8× at system level and 13–43× at kernel level, for accelerated functions such as preprocessing and centroiding. Thus, our HW/SW techniques lead to a star tracker with real-time performance and sufficient accuracy, which enables satellite navigation with more timely attitude determination or considerable decrease in power. The remainder of this paper is structured as follows. Section 2 provides an overview of related works. Section 3 describes the system pipeline and the considered centroiding algorithms, while the proposed hardware designs are explained in Sect. 4. Their evaluation is included in Sect. 5 and the final conclusions are stated in Sect. 6. [6, 30] with the proposals of the Gaussian Grid (GC) and Gaussian Analytic (GA) algorithms. The GC method provides an acceleration of almost 2 orders of magnitude, but it suffers from accuracy loss. GA is as accurate as the 1D GF and as fast as CG, but it is sensitive to noise. The very noise-robust FGF [29] is one of the most promising fitting algorithms for real-time applications, as it is 15× faster than GF without compromising accuracy. Overall, these works show commonly used algorithms, such as clustering and CG [21], as well as the novel FGF that we trade-off in our study. Regarding hardware implementations, Zhou et al. [35] propose a two-step algorithm that detects clusters through zero crossings, enabling high noise robustness, and accelerate it by 23× on a SoC FPGA. In the same context, an FPGAbased implementation of GF is proposed in [12], while the work of [33] proposes a fully custom end-to-end star tracker on FPGA, achieving an update rate of 10Hz. Marcelino et al. [23] propose a method that uses an IIR filter to perform centroiding, which is accelerated by 3.5× when an FPGA is deployed for high-speed image transmission and thresholding. In [2], the proposed ASIC-based hardware architecture performs centroid detection with one image scan, delivering an acceleration of up to 57.5×. The clustering is based on a connected component labeling method and deploys tables that are updated concurrently with the image scan, while CG is used for centroiding. Inspired by this work, Wang et al. [31] propose an one-scan metho (...truncated)