A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator

International Journal of Electrical and Computer Engineering (IJECE) Vol. 13, No. 6, December 2023, pp. 6102~6117 ISSN: 2088-8708, DOI: 10.11591/ijece.v13i6.pp6102-6117  6102 A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator Chutpipat Chaichomnan1,2, Phanumas Khumsat1 1 Department of Electrical Engineering, Faculty of Engineering, Prince of Songkla University, Songkhla, Thailand 2 Silicon Craft Technology, Bangkok, Thailand Article Info ABSTRACT Article history: A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flipflop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18 m digital complementary metal–oxide– semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10-10 and 9.8×10-10, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ. Received Jan 21, 2023 Revised Apr 19, 2023 Accepted Jun 26, 2023 Keywords: Binary phase-shift keying Costas loop Demodulator Phase controller Phase-locked loop Quadrature phase-shift keying Symbol-error rate This is an open access article under the CC BY-SA license. Corresponding Author: Phanumas Khumsat Department of Electrical Engineering, Faculty of Engineering, Prince of Songkla University Hat-Yai, Songkhla, 90110 Thailand Email: 1. INTRODUCTION In and on-human body communication (HBC) has been emerging as an essential development for modern healthcare monitoring and treatment. To achieve a practical implant communication distance and a reasonably high data rate, a 10 to 100 MHz frequency band can be utilized for in-body HBC applications owing to high penetration depth and low path loss [1]–[3]. Regarding a modulation scheme, binary and quadrature phase-shift keying (BPSK, QPSK) can offer a very low bit-error rate (BER) for a given signal-to-noise ratio [1]. BPSK and QPSK have been widely deployed in many communication systems for various applications such as HBC, biomedical data links, wireless radio, and optical data links [4]–[17]. One of the most widely-used BPSK demodulation technique in integrated circuits and systems relies on Costas loop [4], [18] which allows carrier frequency tracking and phase synchronization. With the use of a quadrature voltage-controlled oscillator (VCO) inside a phase-locked loop (PLL), the Costas loop has a deep impact on digital communications for many decades [19]. In research [9], [11], Costas loop has been employed for high data-rate BPSK demodulation in a highspeed wireless link. To improve the Costas loop’s stability, a delay-locked loop (DLL) can be utilized to build a BPSK demodulator as demonstrated in [12], [14] for HBC. Linear multiplication and a quadrature VCO in these Costas loops pose a design challenge, especially at a high-frequency operation. A BPSK or QPSK Journal homepage: http://ijece.iaescore.com Int J Elec & Comp Eng ISSN: 2088-8708  6103 demodulator using a single-phase VCO without any linear multiplier would be truly attractive. The BPSK demodulator in [20] employs a DLL-based clock-data recovery technique (CDR) with a half-rate bang-bang phase detector (BBPD) that directly extracts a synchronized clock signal from the BPSK signal with a dedicated 0/90 signal generator. Extending this technique for higher-order PSK demodulation is possible but with a more complicate design on the CDR loop and the phase detector. A single-phase locked-loop-based BPSK demodulator in [8] is proposed for a biomedical data link. However, the structure still possesses two overlapping loops making the design rather complicate in controlling the loop stability. Another single-phase BPSK demodulator can be found in [15] which employs a phase-frequency detector (PFD) inside a single-loop structure. The demodulation principle practically relies on transition detection where it requires a dedicate data recovery block to obtain demodulated data from the transition detector. For both of these BPSK demodulators, it would be rather difficult to extend these demodulators for QPSK, 8-PSK or m-PSK demodulation. The non-locked-loop BPSK demodulator in [21] utilizes an injection-locking oscillator together with signal addition and amplitude detection for extraction. Although it offers a fairly competitive performance in term of energy-per-bit (Eb), the technique is prone to adjacent channel interference with a rather high bit-error rate (BER) of about 10-3. The all-digital non-locked-loop system in [22] delivers one of the best Eb-based BPSK demodulator’s performance. Its principle is based on generating a data flipping signal whose rising edges indicate the instants when the recovered data should be flipped. The architecture is non-modular and not straightforward to be extended for demodulating high-order PSK signals. The Costas loop can also be effectively extended for QPSK demodulation with additional circuitries to perform a specific phase-control function suitable for QPSK demodulation as in [23]–[26]. The modifications of these QPSK demodulator structures can be found in [9], [12] for high data-rate applications. These demodulators still employ a quadrature VCO where the accuracy of 0/90 phase difference is still eminent in the design. To the authors’ knowledge there is still no 8-PSK demodulator developed from the Costas loop, so its modularity is limited to a certain extent. The QPSK demodulator of the receiver in [16] utilizes a carrier recovery loop (CRL), multiphase generator and I/Q demodulator where a single-phase VCO is only required for down conversion. However, a low data rate of this demodulator from 2.4 GHz carrier results in a rather high Eb value. The non-locked-loop 8-PSK demodulator in [27] implemented with an InP 250 nm DHBT process delivers a very high data rate of 15 Gbps. It employs a comparator and a frequency divider for carrier recovery. However, deployment of the off-chip active circuits such as an amplifier, a bandpass filter and a power detector makes it less attractive and hard to assess the overall power efficiency. In this work, an alternative PLL based m-PSK demodulator employing a single-phase VCO inside a single loop structure is introduced for BPSK and QPSK (...truncated)