FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design

Discover Nano Research FS‑iTFET: advancing tunnel FET technology with Schottky‑inductive source and GAA design Jyi‑Tsong Lin1 · Wei‑Heng Tai1 Received: 26 June 2024 / Accepted: 26 August 2024 © The Author(s) 2024  OPEN Abstract In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal–semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (ION). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SSAVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottkyinductive source, further improves the SSAVG by 49% and achieves a superior ION/IOFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology. Keywords Forkshape · Nanosheet · Schottky barrier · Tunnel field-effect transistor (TFET) · Gate ALL around (GAA) · Heterojunction · Metal–semiconductor interface · Subthreshold swing (SS) · Line tunneling 1 Introduction As semiconductor devices continue to be scaled down and the demand for Internet of Things (IoT) technology and artificial intelligence applications increases, reducing overall power consumption has become a critical and urgent research topic [1]. The Tunnel Field Effect Transistor (TFET) operates based on the minority carrier injection mechanism through Band-To-Band Tunneling (BTBT). Unlike the thermionic emission current in MOSFETs, BTBT current in TFETs results in a more abrupt change in channel potential, offering superior switching characteristics and significantly lower Subthreshold Swing (SS). This makes TFETs highly promising for low-power applications [2]. Given the physical limitations of singlecrystalline MOSFETs, TFETs have the potential to achieve subthreshold swing values much below the thermal limit of This work was supported in part by the Ministry of Science and Technology of Taiwan, R.O.C., under Contact MOST109-2221-E-110-018MY3. * Jyi‑Tsong Lin, ; Wei‑Heng Tai, | 1Department of Electrical Engineering, National Sun YatSen University, Kaohsiung 80424, Taiwan, ROC. Discover Nano (2024) 19:140 | https://doi.org/10.1186/s11671-024-04096-4 Vol.:(0123456789) Research Discover Nano (2024) 19:140 | https://doi.org/10.1186/s11671-024-04096-4 60 mV/dec at room temperature [2–4]. However, the practical application of TFETs is hindered by several challenges such as lower ON-state current (ION) due to minority carrier tunneling and unstable non-ideal effects like Trap-Assisted Tunneling (TAT) and ambipolar behavior, which need to be addressed [5–10]. Enhancing on-current and switching performance can be achieved by using heteromaterial and other methods. Compared to a fully silicon-based structure, introducing a heterojunction between the source and channel areas and using a narrow bandgap material in the source region can shorten the tunneling distance and provide better band-to-band tunneling behavior [11, 12]. Additionally, incorporating a drain region with a wider bandgap material can effectively reduce the device’s leakage current, thereby significantly improving the ON-state/OFF-state current (ION/IOFF) ratio [6]. In traditional P-I-N TFETs, band-to-band tunneling (BTBT) occurs primarily at the interface corner between the source and channel areas, known as point tunneling. This type of tunneling, which is parallel to the channel, is influenced by the local electric field. However, the electric field within the channel is typically continuously changing with channel position, leading to a smaller corner tunneling region and significantly limiting the device’s switching performance. In contrast, utilizing tunneling perpendicular to the channel, known as line tunneling, provides a controllable and expandable tunneling area [13]. Combining this with a metal–semiconductor Schottky source can form a depletion region at the interface, creating the necessary carrier inversion layer to achieve a p–n junction-like effect [6, 14], and establishing a larger and more uniform electric field within the channel. This approach is highly beneficial for enhancing the ION of TFETs, as higher current drive facilitates faster switching speeds and better device performance. As low-power and high-speed devices, TFETs rely significantly on gate-over-channel controllability. Recent studies have demonstrated that integrating Gate-All-Around (GAA) [15, 16] nanosheet structures with TFETs offers excellent potential in terms of scalability [17] and enhanced switching characteristics, achieving an ION/IOFF ratio of ≧105 and an average subthreshold swing (SSAVG) of less than 45 mV/dec [18–21]. Furthermore, due to their vertical-tunneling mechanisms, line-tunneling TFETs can significantly increase the total effective tunneling area by utilizing multiple nanosheets. Nowadays, the term "technology node" symbolizes the overall advancements in manufacturing processes, including factors such as transistor density and performance, rather than a specific feature size, such as fin-width or gate length. In this paper, our design focuses on the channel thickness (tSi), the gate/source overlapping channel length (LG), the channel width (W), and the number of nanosheets, as shown in Table 1. This enhances the efficiency and performance of our integration by optimizing the total tunneling processes. This results in superior efficiency and performance, as the increased overlap area between the source and the gate directly contributes to better device characteristics. Additionally, by integrating these advantages with a Schottky inductive source, it is possible to enhance the ION while maintaining good gate controllability over the channel current. Using calibration-based simulations with Sentaurus TCAD, we propose and integrate a novel Forkshape nanosheet inductive TFET (FS-iTFET) and compare its performance aspects with two newly designed integrations based on the traditional P-I-N TFET structure and the conventional line TFET: the Nanosheet TFET (NS-TFET) and the Nanosheet Line-Tunneling TFET (NS-LTFET). Notably, our newly designed NS-LTF (...truncated)