Development of silicon-on-insulator direct electron detector with analog memories in pixels for sub-microsecond imaging

Microscopy, 2024, 73(6), 511–516 DOI: https://doi.org/10.1093/jmicro/dfae029 Advance Access Publication Date: 1 June 2024 Article Development of silicon-on-insulator direct electron detector with analog memories in pixels for sub-microsecond imaging Takafumi Ishida 1,2,* , Kosei Sugie2 , Toshinobu Miyoshi3,† , Yuichi Ishida4 , Koh Saitoh1,2 , Yasuo Arai5 and Makoto Kuwahara 1,2 Institute of Materials and Systems for Sustainability, Nagoya University, Furo-cho, Chikusa, Nagoya 464-8601, Japan Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa, Nagoya 464-8601, Japan 3 Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba 305-0801, Japan 4 School of Engineering, Nagoya University, Furo-cho, Chikusa, Nagoya 464-8601, Japan 5 Accelerator Laboratory, High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba 305-0801, Japan 2 * † To whom correspondence should be addressed. E-mail: T. M. has retired from KEK. Abstract We have developed a high-speed recordable direct electron detector based on silicon-on-insulator technology. The detector has 16 analog memories in each pixel to record 16 images with sub-microsecond temporal resolution. A dedicated data acquisition system has also been developed to display and record the results on a personal computer. The performance of the direct electron detector as an image sensor is evaluated under electron irradiation with an energy of 30 keV in a low-voltage transmission electron microscope equipped with a photocathode electron gun. We demonstrate that the detector can record images at an exposure time of 100 ns and an interval of 900 ns. Key words: SOI pixel detector, back-side illumination, high-speed imaging, pulsed electrons Introduction The development of direct electron detectors (DEDs) has played a role in improving the quality of images acquired using transmission electron microscopes [1,2]. In particular, DEDs are critical for observing biological and organic specimens via transmission electron microscopy (TEM) [3,4] because such specimens require low-dose, high-resolution and high-speed imaging to reveal their fine structures. In addition, DEDs, which have single electron counting capability, are useful for ultra-fast imaging by time-resolved transmission electron microscopy (TR-TEM) [5] because the improvement in temporal resolution is usually accompanied by a decrease in the number of detected electrons. The single electron counting capability of DEDs will also lead the signal-to-noise ratio of images to the theoretical limit in TR-TEM. The usefulness of DEDs stems from their high detection efficiency, high modulation transfer function (MTF) and high read-out speed compared with those of traditional detectors with scintillators, such as charge-coupled device cameras [6]. Their high detection efficiency originates from the high number of generated charges at the sensor layer by primary electrons with high energy. Their high MTF was realized by thinning the sensor thickness and post-processing based on single electron counting. On the other hand, their read-out speed depends on the read-out method, and most DEDs are based on complementary metal oxide semiconductor (CMOS) technology. The read-out speed of DEDs depends on the number of pixels and restricts their frame rates. The number of parallel read-outs from the detectors is limited by the performance of data acquisition (DAQ) systems, which consist of readout circuits and a personal computer (PC). The frame rate of commercial DEDs decreases with increasing pixel number [7–9]. For example, the minimum repetition time, which corresponds to the frame period, is approximately 0.5 ms at 1 Mpixels (1024 × 1024 pixels) [8]. Current DEDs cannot be used to observe nonreversible phenomena that occur on a sub-microsecond timescale. We can overcome the frame rate limitation of the DAQ system by using a special chip design. In optical cameras, a frame rate greater than 100 Mfps has been achieved by Suzuki et al. [10], who incorporated a memory array into the sensor chip. This principle can be briefly explained as follows: The signal obtained in each pixel is quickly transferred to the memory array on the chip, and the signal is then slowly read out from the chip by a DAQ system. The aforementioned frame rate limitation is avoided by preserving the signal in the chip, and the recording length of the number of frames is restricted by the density of the memory array in the chip. Received 29 March 2024; Revised 30 April 2024; Editorial Decision 27 May 2024; Accepted 30 May 2024 © The Author(s) 2024. Published by Oxford University Press on behalf of The Japanese Society of Microscopy. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse, distribution, and reproduction in any medium, provided the original work is properly cited. 1 512 T. Ishida et al. Development of an SOI detector for sub-microsecond imaging SOI device and experimental setup SOI pixel detector with analog memories We have developed a novel SOI direct electron detector, named the silicon-on-insulator for time-resolved imaging in electron microscopy (STRIEM), which is capable of sub-microsecond imaging. Figure 1 shows a cross-sectional schematic of the STRIEM, an optical micrograph image of the STRIEM ver. 1 (hereafter called STRIEM1) chip and a schematic of the chip layout. The structure of the STRIEM (Fig. 1(a)), in which the CMOS circuit and the sensor layers are bonded through the insulator, is the same as that of conventional SOI pixel detectors. The chip shown in Fig. 1(b), which has one polysilicon and five metal layers, was fabricated in a 0.2-μm SOI–CMOS process by Lapis Semiconductor Co., Ltd. The wafer for the sensor was a p-type silicon wafer with a high resistivity of ∼5 kΩ⋅ cm. The sensor layer was thinned to 300 μm, followed by deposition of aluminum to a thickness of 200 nm. The aluminum layer functions as an electrode for the application of a bias voltage used to fully deplete the sensor layers. Here, the full depletion voltage of the sensor layer was estimated at approximately −180 V from the resistivity and the thickness. The chip had 28 × 28 pixels within a 1.4 × 1.4 mm2 area (pixel size 50 × 50 μm2 ) with peripheral circuits. The main peripheral circuits are address decoders to read out a pixel value and a column buffer to connect the pixels to an output terminal (Fig. 1(b)). Figure 2 shows a pixel circuit of the SOI DED with analog memories (STRIEM1). The switch and input voltage names are displayed near these elements. Each pixel has 16 capacitors (C_S) consisting of metal-insulator-metal (MIM) capacitors in the metal layers to recode the detected voltage with a correlated double sampling (CDS) circuit (the switch CDS_RST and the capacitor C_CDS) that can cancel the reset n (...truncated)