Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

Majlis BY (2013) Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET. PLoS ONE 8(12): e82731. doi:10.1371/journal.pone.0082731 Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET Mohd F. Mohd Razip Wee 0 Arash Dehzangi 0 Sylvain Bollaert 0 Nicolas Wichmann 0 Burhanuddin Y. Majlis 0 Sefer Bora Lisesivdin, Gazi University, Turkey 0 1 Institute of Electronics , Microelectronics and Nanotechnology (IEMN) , University Lille 1, Villeneuve d'Ascq, France, 2 Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia , Bangi, Selangor , Malaysia A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 mm and 30mm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 1028 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. - Funding: The authors gratefully acknowledge that this work was financially supported by the National of Research Agency of France (MOS35 project, ANR-08NANO-022) and Universiti Kebangsaan Malaysia through the grant project with the code of Dana Impac Perdana, DIP-2012-16. The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. Competing Interests: The authors have declared that no competing interests exist. The continuous scaling of MOS devices leads to some fundamental limits such as short channel effects (SCEs) and high leakage current related to having lower gate controllability on the channel. This can make a crucial challenge against the performance improvements of the scaled devices mentioned by the International Technology Roadmap of Semiconductors (ITRS). To conquer this limitations, several new technologies such as highk dielectrics [1], metal gate electrodes [2], stressors [3], and new transistor architectures based on silicon-on-insulator (SOI), such as Fin FETs [4], Junctionless transistors [5] or gate-all-around FETs [6], have been proposed. Another important option, in order to overcome the scaling limitation, is to seek any possible alternative of beyond Si channel materials, such as Germanium and IIIV compound semiconductors. In this matter, ternary IIIV compound InGaAs is considered as a reliable material for future CMOS devices, regarding to its high electron mobility, saturation velocity, achievable band gap engineering and narrow band gap in comparison with the Si or GaAs base device counterparts. In fact, reduction of gate dimension requires decrease of the oxide thickness, which may lead to unwanted gate leakage current. In order to reduce gate current, high permittivity (high-k) dielectrics has been considered with the ability of being ultrathin insulator beyond the SiO2 probable limitations. The proper high-k dielectric material must be thermally stable up to 1000 u C since it is subjected to annealing at high temperature during the fabrication process of the transistor. Recently, the development of atomic-layer-deposited (ALD) technology has provided a promising result for depositing ultra-small thickness of the oxide layers. As a proper candidate for dielectrics on III-V semiconductors, several dielectrics has been recently proposed, such as ALD Al2O3 [7,8], HfO2 [9] or HfAlO [10]. Some high performance devices have been reported for self-aligned InGaAs MOSFETs with high-k gate dielectrics formed by ALD [11,12,13]. A gate-first self-aligned process is required to reach high speed logic devices by reducing overlap capacitance and series resistance [14]. Lower series resistance can supress loss of the drain current by decreasing the gate and source/drain misalignment. Moreover, a gate-first method has less complication at fabrication process in comparison with the gate-last process. However, the gate-first process imposes more thermal budget over the device and introduces larger interface trap density between the high-k /InGaAs interface. Due to the higher resilience against the drain induced-barrierlowing effects or leakage problems, the inversion type MOSFETs are more preferred than depletion type MOSFETs with buriedchannel [7]. In previous work [15], the fabrication of inversion type In0.53Ga0.47As MOSFET with 8 nm Al2O3 gate oxide thickness, using ALD, was briefly reported. It is found that the devices with Al2O3 oxide layer has less interface trap density (Dit) compare to the ones with HfO2 [7]. Moreover, Al2O3 has a high band gap (,9 eV), a high-breakdown electric field (530 MV/ cm), and a satisfactory result in terms of equivalent oxide thickness (EOT) with high thermal stability (up to at least 1000uC) [8]. In most of the reported cases for self-aligned InGaAs MOSFETs, it was used refractory metals as the gate metal in fabrication process. The gate material used in this work is Tantalum (Ta) whose high resistivity value (1.861026 Vm) can interrupt extraction of accurate small signal equivalent circuit. To avoid this problem a multi-gate technology is implemented to define multi fingers for present work. In multi finger structure the gate resistance is decreased by the factor of 1/n2, where n in the number of fingers. The devices have 8 fingers with the air bridge to connect all the sources in coplanar topology. In this work, the fabrication process of inversion mode n-type In0.53Ga0.47As MOSFET is elaborately addressed and the electrical characterization of the device is developed. The impact of length variation on threshold voltage, high and low drain voltage transconductance, output characteristics, gate leakage current and field effect mobility are demonstrated. Threshold voltages, subthreshold swing, off drain current and gate to source/ drain overlap length are extracted and compared for all devices with different lengths down to 200 nm. Finally, the RF results for cut-off and maximum oscillation frequency of devices with different gate lengths are shown and compared. The schematic flow of fabrication for self-aligned n-type In0.53Ga0.47As MOSFET is illustrated in Fig 1. The devices fabrication began with a molecular beam epitaxy (MBE model RIBER 32P) (...truncated)