Enhanced efficiency of crystalline Si solar cells based on kerfless-thin wafers with nanohole arrays
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Received: 11 September 2017
Accepted: 31 January 2018
Published: xx xx xxxx
Enhanced efficiency of crystalline
Si solar cells based on kerfless-thin
wafers with nanohole arrays
Hyeon-Seung Lee1,2, Jaekwon Suk3, Hyeyeon Kim3, Joonkon Kim3, Jonghan Song3,
Doo Seok Jeong 1, Jong-Keuk Park1, Won Mok Kim1, Doh-Kwon Lee4, Kyoung Jin Choi5,
Byeong-Kwon Ju2, Taek Sung Lee1 & Inho Kim1
Several techniques have been proposed for kerfless wafering of thin Si wafers, which is one of the most
essential techniques for reducing Si material loss in conventional wafering methods to lower cell cost.
Proton induced exfoliation is one of promising kerfless techniques due to the simplicity of the process
of implantation and cleaving. However, for application to high efficiency solar cells, it is necessary to
cope with some problems such as implantation damage removal and texturing of (111) oriented wafers.
This study analyzes the end-of-range defects at both kerfless and donor wafers and ion cutting sites.
Thermal treatment and isotropic etching processes allow nearly complete removal of implantation
damages in the cleaved-thin wafers. Combining laser interference lithography and a reactive ion etch
process, a facile nanoscale texturing process for the kerfless thin wafers of a (111) crystal orientation
has been developed. We demonstrate that the introduction of nanohole array textures with an optimal
design and complete damage removal lead to an improved efficiency of 15.2% based on the kerfless
wafer of a 48 μm thickness using the standard architecture of the Al back surface field.
Si wafers for crystalline Si solar cells, produced by multi-wire sawing the Si ingot grown by a Czochralski method,
have been consistently thinner to lower cell cost by reducing material consumption1–3. The thickness of Si wafers
can be reduced by using multi-wire saws of smaller diameters4. However, it is known that a minimum thickness
of Si wafers manufactured by a multi-wire sawing method is limited to approximately 80 μm. This is because a
wafering yield is greatly reduced and the Si wastes are considerable when a Si wafer becomes thinner. In this
regard, there has been numerous efforts to fabricate thin Si wafers below 50 μm with negligible wafering material
losses, and this technique is termed kerfless wafering5.
Several kerfless wafering techniques have been proposed: epitaxial Si lift-off, stress-induced spalling, and
smart-cut. Using an epitaxial Si lift-off technique, a thin wafer is epitaxially grown on a porous seed Si wafer by
atmospheric chemical deposition (APCVD) and exfoliated from the parent seed wafer6–10. Epitaxial growth of
high quality Si wafers, comparable to high performance CZ wafers, was demonstrated, and high efficiency of
21.2% based on a 35 μm thickness Si wafer was achieved11. However, this technique has high process complexity
due to the production of porous Si and requires faster Si growth rates for commercialization. Many research
works are underway in order to tackle these issues12. The stress-induced technique or SLIM-cut employs a stress
induced layer on the Si wafer, and the stress is activated by thermal expansion mismatch between the stress layer
and the Si wafer for spalling of thin wafers13. Recently, a novel method of electrodeposit-assisted stripping (EAS)
has been developed to minimize the formation of micro-structural defects during the SLIM-cut process14. In
the EAS process, a thin stress layer is electro-deposited at room temperature, and the lattice mismatch between
the stress layer and the wafer induces a large stress field, which causes the lift-off of a thin Si wafer without high
temperature annealing.
Another kerfless wafering technique based on a smart cut technique invented in 1990’s was attempted to
fabricate kerfless wafers of tens of micrometer thickness for Si solar cells using a MeV proton implanter15,16. In
1
Center for Electronic Materials, Korea Institute of Science and Technology, Seoul, 02792, Republic of Korea.
School of Electrical Engineering, Korea University, Seoul, 02841, Republic of Korea. 3Advanced Analysis Center,
Korea Institute of Science and Technology, Seoul, 02792, Republic of Korea. 4Photo-electronic Hybrids Research
Center, Korea Institute of Science and Technology, Seoul, 02792, Republic of Korea. 5School of Materials Science
and Engineering, Ulsan National Institute of Science and Technology (UNIST), Ulsan, 44919, South Korea.
Correspondence and requests for materials should be addressed to I.K. (email: )
2
SCientifiC REPOrts | (2018) 8:3504 | DOI:10.1038/s41598-018-21381-2
1
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this technique, a proton beam with a MeV energy is implanted into donor wafers17. The implanted protons are
penetrated into a certain depth of the donor wafers depending on the proton acceleration energy. The implanted
wafers are subsequently annealed to be exfoliated by hydrogen micro-bubble formation and crack propagation18,19. The proton induced exfoliation technique is a relatively simple and clean vacuum process compared with
the epitaxial Si lift-off method20. In this technique, a critical proton dose for exfoliation of thin wafers relies on the
crystal orientation of the parent Si wafers. The (111) Si surface has the lowest surface energy per unit area and in
turn, the lowest fracture toughness; thus, the lowest critical proton dose is required for the kerfless wafering of the
(111) Si wafers. Because the critical ion dose is directly related with manufacturing throughput time, the wafering
of the (111) crystal orientation is most economically feasible. This limitation in the choice of crystal orientation
pose challenges in light trapping and surface passivation. Also, the ion implanter of MV acceleration voltage and
mA ion current is required for fabrication of the ultra-thin wafers with a thickness of 20 to 50 μm. The relatively
high cost of special proton implanter compared with other wafering methods is one of the barriers for the commercialization of the proton induced exfoliation technique.
The implanted protons collide with Si host atoms while penetrating the donor wafer, losing the acceleration
energy, resulting in creation of structural defects21. Most of the defects generated near the implantation surface of
the wafer are easily removed by thermal annealing20. However, secondary defects such as dislocation loops and
platelets formed at the ends of projected ranges are hardly removed20–23. For this reason, such defects are removed
by etching a specific thickness of the cleaved wafers. Because the formation of the secondary defects leads to Si
material losses, a thickness of the secondary defect zone induced implantation needs or end-of-range (EOR)
defect zone to be analyzed21. However, a rare study on the EOR defect zone thickness induced by the MeV accelerated proton beams has been reported. Furthermore, the reported efficiency of Si solar cells based on kerfless (...truncated)